Unnamed repository; edit this file 'description' to name the repository. http://euandre.org/git/grovel/atom?h=main 2023-02-11T15:00:31Z 2023-02-11T15:00:31Z Rich Felker dalias@aerifal.cx 2023-02-11T14:43:29Z urn:sha1:115149c023485a69f5bff05efd5339c0c5f77798 the logic to check hwcap for SPE register file inadvertently clobbered the val argument before use. switch to a different work register so this doesn't happen. 2021-11-29T22:41:43Z Rich Felker dalias@aerifal.cx 2021-11-29T22:41:43Z urn:sha1:8274aaaaa1948c50c661aa32e21b3db27a5c0eab commit 7be59733d71ada3a32a98622507399253f1d5e48 introduced the hwcap-based branches to support the SPE FPU, but wrongly coded them as bitwise tests on the computed address of __hwcap, not a value loaded from that address. replace the add with indexed load to fix it. 2021-09-23T23:11:46Z Rich Felker dalias@aerifal.cx 2021-09-23T23:11:46Z urn:sha1:7be59733d71ada3a32a98622507399253f1d5e48 When the soft-float ABI for PowerPC was added in commit 5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb, with Freescale cpus using the alternative SPE FPU as the main use case, it was noted that we could probably support hard float on them, but that it would involve determining some difficult ABI constraints. This commit is the completion of that work. The Power-Arch-32 ABI supplement defines the ABI profiles, and indeed ATR-SPE is built on ATR-SOFT-FLOAT. But setjmp/longjmp compatibility are problematic for the same reason they're problematic on ARM, where optional float-related parts of the register file are "call-saved if present". This requires testing __hwcap, which is now done. In keeping with the existing powerpc-sf subarch definition, which did not have fenv, the fenv macros are not defined for SPE and the SPEFSCR control register is left (and assumed to start in) the default mode. 2016-03-06T22:03:01Z Felix Fietkau nbd@openwrt.org 2016-01-25T12:20:52Z urn:sha1:5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different instruction set for floating point operations (SPE). Executing regular PowerPC floating point instructions results in "Illegal instruction" errors. Make it possible to run these devices in soft-float mode. 2015-04-20T01:20:08Z Rich Felker dalias@aerifal.cx 2015-04-20T01:20:08Z urn:sha1:cf1a9d9d16a79322df15b344a2617b79ebb12705 these are perfectly fine with ld-time symbol binding, but otherwise result in textrels. they cannot be replaced with @PLT jump targets because the PLT thunks require a GOT register to be setup, so use a hidden alias instead. 2012-11-23T19:30:58Z Rich Felker dalias@aerifal.cx 2012-11-23T19:30:58Z urn:sha1:a50136dfe186a3ea3d78a4264187915ad16ab861 2012-11-14T19:27:51Z Rich Felker dalias@aerifal.cx 2012-11-14T19:27:51Z urn:sha1:d1bf452d75bef2b098765fe94b9ccb24cdb6568b 2012-11-13T18:12:25Z rofl0r retnyg@gmx.net 2012-11-09T22:36:55Z urn:sha1:1c8eb8bad791fe9d01d0d4ab77882db634fa933d